Design of an Efficient Interconnection Network of Temperature Sensors

Temperature has become a first class design constraint because high temperatures adversely affect circuit reliability, static power and degrade the performance. In this scenario, thermal characterization of ICs and on-chip temperature monitoring represent fundamental tasks in electronic design. In this work, we analyze the features that an interconnection network of temperature sensors must fulfill. Departing from the network topology, we continue with the proposal of a very light-weight network architecture based on digitalization resource sharing. Our proposal supposes a 16% improvement in area and power consumption compared to traditional approache

Hardware Reuse Improvement through the Domain Specific Language dHDL.

The dHDL language has been defined to improve hardware design productivity. This is achieved through the definition of a better reuse interface (including parameters, attributes and macroports) and the creation of control structures that help the designer in the hardware generation process

Impedance Spectroscopy Study of the Effect of Environmental Conditions on the Microstructure Development of Sustainable Fly Ash Cement Mortars

Today, the characterisation of the microstructure of cement-based materials using non-destructive techniques has become an important topic of study, and among them, the impedance spectroscopy has recently experienced great progress. In this research, mortars with two different contents of fly ash were exposed to four different constant temperature and relative humidity environments during a 180-day period. The evolution of their microstructure was studied using impedance spectroscopy, whose results were contrasted with mercury intrusion porosimetry. The hardening environment has an influence on the microstructure of fly ash cement mortars. On one hand, the impedance resistances R1 and R2 are more influenced by the drying of the materials than by microstructure development, so they are not suitable for following the evolution of the porous network under non-optimum conditions. On the other hand, the impedance spectroscopy capacitances C1 and C2 allow studying the microstructure development of fly ash cement mortars exposed to those conditions, and their results are in accordance with mercury intrusion porosimetry ones. Finally, it has been observed that the combined analysis of the abovementioned capacitances could be very useful for studying shrinkage processes in cement-based materials kept in low relative humidity environments.This work has been financially supported by the “Ministerio de Economía y Competitividad” (formerly “Ministerio de Ciencia e Innovación”) of Spain and FEDER through project BIA2011-25721

On-chip Monitoring: A Light-Weight Interconnection Network Approach

Current nanometer technologies are subjected to several adverse effects that seriously impact the yield and performance of integrated circuits. Such is the case of within-die parameters uncertainties, varying workload conditions, aging, temperature, etc. Monitoring, calibration and dynamic adaptation have appeared as promising solutions to these issues and many kinds of monitors have been presented recently. In this scenario, where systems with hundreds of monitors of different types have been proposed, the need for light-weight monitoring networks has become essential. In this work we present a light-weight network architecture based on digitization resource sharing of nodes that require a time-to-digital conversion. Our proposal employs a single wire interface, shared among all the nodes in the network, and quantizes the time domain to perform the access multiplexing and transmit the information. It supposes a 16% improvement in area and power consumption compared to traditional approaches

A Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration

Current nanometer technologies suffer within-die parameter uncertainties, varying workload conditions, aging, and temperature effects that cause a serious reduction on yield and performance. In this scenario, monitoring, calibration, and dynamic adaptation become essential, demanding systems with a collection of multi purpose monitors and exposing the need for light-weight monitoring networks. This paper presents a new monitoring network paradigm able to perform an early prioritization of the information. This is achieved by the introduction of a new hierarchy level, the threshing level. Targeting it, we propose a time-domain signaling scheme over a single-wire that minimizes the network switching activity as well as the routing requirements. To validate our approach, we make a thorough analysis of the architectural trade-offs and expose two complete monitoring systems that suppose an area improvement of 40% and a power reduction of three orders of magnitude compared to previous works

A Monitoring Infrastructure for FPGA Self-Awareness and Dynamic Adaptation

Variabilities associated with CMOS evolution affect the yield and performance of current digital designs. FPGAs, which are widely used for fast prototyping and implementation of digital circuits, also suffer from these issues. Proactive approaches start to appear to achieve self-awareness and dynamic adaptation of these devices. To support these techniques we propose the employment of a multi-purpose sensor network. This infrastructure, through adequate use of configuration and automation tools, is able to obtain relevant data along the life cycle of an FPGA. This is realised at a very reduced cost, not only in terms of area or other limited resources, but also regarding the design effort required to define and deploy the measuring infrastructure. Our proposal has been validated by measuring inter-die and intra-die variability in different FPGA families

Bullying in Adolescents Practising Sport: A Structural Model Approach

This article aims to analyse the relationship between the bullying aggressor and bullying victim profile related to practising or not practising sport in adolescents living in southern Spain. The research includes male and female participants aged between 12 and 16 years in different secondary schools in the provinces of Andalusia, Ceuta and Melilla in the period between February 2022 and June 2022. The study aims to extend the existing scientific, theoretical and empirical knowledge on the influence of playing sport or not on disruptive bullying attitudes in adolescents. To this end, two initial hypotheses were designed; the first hypothesises that bullying victim behaviours are associated with future bullying aggressor behaviours when practising sport; and the second states that victim behaviours are associated with future bullying aggressor behaviours when not practising sport. To verify them, SPSS software was used for the preliminary analysis of the scale and sociodemographic profile. Additionally, the study is based on structural equation modelling methodology and variance-based methods employing SmartPLS v3.3 software. The results show the importance of sport or physical activity to reduce the chances of carrying out bullying actions on other peers and/or classmates. Therefore, it is considered necessary to prevent bullying in the classroom by implementing sports intervention programmes in educational centres

Area-Efficient Linear Regression Architecture for Real-Time Signal Processing on FPGAs

Linear regression is a technique widely used in digital signal processing. It consists on finding the linear function that better fits a given set of samples. This paper proposes different hardware architectures for the implementation of the linear regression method on FPGAs, specially targeting area restrictive systems. It saves area at the cost of constraining the lengths of the input signal to some fixed values. We have implemented the proposed scheme in an Automatic Modulation Classifier, meeting the hard real-time constraints this kind of systems have

Improving Hardware Reuse through XML-based Interface Encapsulation

This work proposes an encapsulation scheme aimed at simplifying the reuse process of hardware cores. This hardware encapsulation approach has been conceived with a twofold objective. First, we look for the improvement of the reuse interface associated with the hardware core description. This is carried out in a first encapsulation level by improving the limited types and configuration options available in the conventional HDLs interface, and also providing information related to the implementation itself. Second, we have devised a more generic interface focused on describing the function avoiding details from a particular implementation, what corresponds to a second encapsulation level. This encapsulation allows the designer to define how to configure and use the design to implement a given functionality. The proposed encapsulation schemes help improving the amount of information that can be supplied with the design, and also allow to automate the process of searching, configuring and implementing diverse alternatives

Implementing FFT-based digital channelized receivers on FPGA platforms

This paper presents an in-depth study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed in depth, revealing interesting implementation trade-offs which should be taken into account when designing this kind of signal processing systems on FPGA platforms